6. Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device
will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a high-
to-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be
automatically selected on every falling edge of CS by sampling the inactive clock state. After
power is applied and V CC is at the minimum datasheet value, the system should wait 20 ms
before an operational mode is started.
Table 6-1.
Detailed Bit-level Addressing Sequence
Address Byte
Address Byte
Address Byte
Additional
Don’t Care
Bytes
Opcode
Opcode
Required
50H
52H
53H
54H
55H
56H
0 1 0 1 0 0 0 0 r
0 1 0 1 0 0 1 0 r
0 1 0 1 0 0 1 1 r
0 1 0 1 0 1 0 0 x
0 1 0 1 0 1 0 1 r
0 1 0 1 0 1 1 0 x
r
r
r
x
r
x
r
r
r
x
r
x
r
r
r
x
r
x
P
P
P
x
P
x
P
P
P
x
P
x
P
P
P
x
P
x
P
P
P
x
P
x
P
P
P
x
P
x
P
P
P
x
P
x
P
P
P
x
P
x
P
P
P
x
P
x
x
P
P
x
P
x
x
P
P
x
P
x
x
P
P
x
P
x
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
N/A
4 Bytes
N/A
1 Byte
N/A
1 Byte
57H
0 1 0 1 0 1 1 1
N/A
N/A
N/A
N/A
58H
59H
60H
61H
68H
81H
82H
83H
84H
85H
86H
87H
88H
89H
D2H
D4H
D6H
0 1 0 1 1 0 0 0 r
0 1 0 1 1 0 0 1 r
0 1 1 0 0 0 0 0 r
0 1 1 0 0 0 0 1 r
0 1 1 0 1 0 0 0 r
1 0 0 0 0 0 0 1 r
1 0 0 0 0 0 1 0 r
1 0 0 0 0 0 1 1 r
1 0 0 0 0 1 0 0 x
1 0 0 0 0 1 0 1 r
1 0 0 0 0 1 1 0 r
1 0 0 0 0 1 1 1 x
1 0 0 0 1 0 0 0 r
1 0 0 0 1 0 0 1 r
1 1 0 1 0 0 1 0 r
1 1 0 1 0 1 0 0 x
1 1 0 1 0 1 1 0 x
r
r
r
r
r
r
r
r
x
r
r
x
r
r
r
x
x
r
r
r
r
r
r
r
r
x
r
r
x
r
r
r
x
x
r
r
r
r
r
r
r
r
x
r
r
x
r
r
r
x
x
P
P
P
P
P
P
P
P
x
P
P
x
P
P
P
x
x
P
P
P
P
P
P
P
P
x
P
P
x
P
P
P
x
x
P
P
P
P
P
P
P
P
x
P
P
x
P
P
P
x
x
P
P
P
P
P
P
P
P
x
P
P
x
P
P
P
x
x
P
P
P
P
P
P
P
P
x
P
P
x
P
P
P
x
x
P
P
P
P
P
P
P
P
x
P
P
x
P
P
P
x
x
P
P
P
P
P
P
P
P
x
P
P
x
P
P
P
x
x
P
P
P
P
P
P
P
P
x
P
P
x
P
P
P
x
x
P
P
P
P
P
P
P
P
x
P
P
x
P
P
P
x
x
P
P
P
P
P
P
P
P
x
P
P
x
P
P
P
x
x
P
P
P
P
P
P
P
P
x
P
P
x
P
P
P
x
x
x
x
x
x
B
x
B
x
B
B
x
B
x
x
B
B
B
x
x
x
x
B
x
B
x
B
B
x
B
x
x
B
B
B
x
x
x
x
B
x
B
x
B
B
x
B
x
x
B
B
B
x
x
x
x
B
x
B
x
B
B
x
B
x
x
B
B
B
x
x
x
x
B
x
B
x
B
B
x
B
x
x
B
B
B
x
x
x
x
B
x
B
x
B
B
x
B
x
x
B
B
B
x
x
x
x
B
x
B
x
B
B
x
B
x
x
B
B
B
x
x
x
x
B
x
B
x
B
B
x
B
x
x
B
B
B
x
x
x
x
B
x
B
x
B
B
x
B
x
x
B
B
B
N/A
N/A
N/A
N/A
4 Bytes
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4 Bytes
1 Byte
1 Byte
D7H
1 1 0 1 0 1 1 1
N/A
N/A
N/A
N/A
E8H
1 1 1 0 1 0 0 0 r
r
r
r
P
P
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
4 Bytes
Note:
12
r = Reserved Bit
P = Page Address Bit
B = Byte/Buffer Address Bit
x = Don’t Care
AT45DB041B
3443D–DFLSH–2/08
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